1. Field of the Invention
This invention relates generally to a process for fabricating semiconductor devices, and more particularly to a high yield process for fabricating integrated circuits having bipolar transistors and other circuit elements.
2. Description of the Prior Art
A fundamental circuit element of bipolar integrated circuits is an npn transistor. Structurally, a bipolar npn transistor has an N type collector and an N type emitter separated by a P type base. According to standard design practice, the collector is an island of N type material located on top of a P type substrate; the base is an island of P type material located within the collector; and the emitter is an island of N type material located within the base. Electrical contacts to the collector, emitter, and base regions are made from the top of the wafer. A low resistivity buried layer located under the base and collector contact minimizes the internal resistance of the collector. The collector region is an N type epitaxial layer formed on top of the P type substrate. The collector region is isolated from adjacent devices, usually by either a P type isolation region or by a region of silicon dioxide.
Integrated circuits used in linear circuit applications generally utilize npn transistors having high current gain and high breakdown voltages, while also having good high frequency response and high signal to noise ratio. Unfortunately, these desirable performance characteristics are often difficult to achieve in combination because an improvement in one characteristic may cause a deterioration in another.
In addition to performance considerations, another consideration in fabricating semiconductor devices is circuit density. Higher circuit density allows more devices to be fabricated on a single wafer, thereby lowering the cost of individual circuits. One factor adversity affecting circuit density is lateral diffusion of doped regions. High temperature processing after the creation of doped regions causes the doped regions to diffuse laterally. Spacing the circuit elements to allow for this lateral diffusion decreases circuit density. Another factor adversely affecting circuit density is mask alignment tolerances. Many circuit features are defined by several masks, each of which must be aligned with respect to previous masks. The alignment tolerance requires that features be larger (by an amount equal to the alignment tolerance) to accommodate the positional uncertainty of subsequent masks.
Another consideration particularly important in making bipolar devices is the fabrication of the base region of npn transistors. In fabricating an npn transistor, it is common to use two implantation steps to form the base region of the transistor. It is known that subsequent thermal oxidation of a wafer that has been heavily doped by ion implantation will cause dislocations and stacking faults to grow in the base region. Such defects adversely affect the performance of the transistor. To avoid this problem, it is common to implant the base region in two steps, first with a low dosage and then with a higher dosage, with a thermal oxidation step performed in between the implantation steps.